Physical design

Layout: placement images rendered from GDSII

Every image below was rasterized layer by layer from the delivered GDSII database itself (ppu65_chip.gds and the block GDS files); none of them is a drawing or a schematic. The dummy-fill layers are switched off in the images.

Full chip Floorplan Analog blocks Digital block Verification (sign-off)Dummy fill

Full chip: ppu65_chip

Full-chip layout — 2600 × 1870 µm inside the seal ring. Top: the digital-core strip (yellow/purple standard cells); centre: the 16 × 34 column-interleaved synapse array (yellow M5 trunks); left: the reference corner and trim multiplexers; right: the conveyor / fold / comparator strip and the noise chain; bottom: the test mux and ESD clamps. The cream squares are the AP (aluminium pad) layer.

OD (diffusion)PO (poly) M1M2M3 M4M5M6 M7M8M9 AP (pad metal)

2.60 × 1.87 mmchip area inside the seal ring

2.847 × 2.051 mmdie (seal ring included)

9 + APmetal layers

67bond pads, 80 µm pitch

292GDS structures (unfilled)

Floorplan

The analog tile and the digital core were designed as separate blocks and assembled at the top level. Placement principles:

Column-interleaved P/N array: the two planes are not stacked but interleaved column by column (physical column 2p = P_j, 2p+1 = N_j). All banks share one orientation (matching), P/N are neighbours (differential), one SL net per plane.
SL star node: the source lines of both planes reach the conveyor strip by the shortest path; SLP/SLN M4 row rails plus 10 µm M5 trunks on the right edge.
Matching inside a bank: the six legs are common-centroid; the VBIAS gate line is distributed along the row in metal.
Noise chain kept away from the array's switching noise, guard-ringed; short injection lines.
Reference corner: bandgap PNPs (1:8 common-centroid), a single serpentine poly string (391 µm), trim multiplexers adjacent.
Power domains: AVDD 2.5 V, VDD 1.2 V, AVDD_REF 2.5 V, VWL 1.0 V; four separate meshes, star connection on the board.

Block	Size (µm)	Contents
ppu_tile (analog tile)	≈ 1773 × 1212	544 synapse banks, row multiplexers, conveyors, fold, comparator, noise chain
ppu_synapse6 (bank)	42.5 × 61.05	63 unit legs (6 binary-weighted groups), SL/BL M3 spines 1.2 µm (EM)
ppu_noise_therm2	≈ 248 × 144	3 gain stages + steerer; ≈ 800 µm of poly resistor
ppu_bandgap	≈ 223 × 142	PNP 1:8 common-centroid, start-up, 0.927 V reference
ppu_ref_rails	≈ 353 × 768	391 µm poly string, 7 trim multiplexers, 7 buffers
ppu_vg_conveyor	≈ 191 × 115	Current conveyor holding SL at 0.150 V (×2)
ppu_fold_sa	≈ 66 × 36	Fold mirrors + StrongARM comparator
ppu_digital_top	≈ 1378 × 244	Synthesised digital core (SPI, register file, sequencer, spin register, weight latches)
ppu_pad_ring	2600 × 1800	67 pads, ESD diodes, 4 power clamps, corner cells

Analog blocks

Each block was rendered from its own GDS file. The colours follow the layer palette above.

Analog tile layout — **ppu_tile** — the 544-bank array (the yellow M5 trunks carry the weight-bit lines per column), the conveyor + fold + comparator strip on the right, the noise chain at the bottom.

Synapse bank layout — **ppu_synapse6** — one bank: 63 identical unit legs (7 × 9) wired into binary-weighted groups. SL/BL M3 spines on the left and right.

Noise-chain layout — **ppu_noise_therm2** — the thermal-noise chain. The long red serpentines are the poly load resistors; the steerer's degeneration ladder is on the right.

Bandgap layout — **ppu_bandgap** — the 0.927 V reference: 1:8 common-centroid PNP array (green squares) and poly resistors.

Conveyor layout — **ppu_vg_conveyor** — the current conveyor: 240 µm legs, error amplifier and compensation capacitor.

Fold and comparator layout — **ppu_fold_sa** — fold mirrors (the BSENSE node) and the StrongARM comparator; one decision per slot.

Comparator latch layout — **ppu_comp_latch** — the latch that captures the comparator output at the strobe (≈ 14 × 13 µm).

Pad-ring layout — **ppu_pad_ring** — the AP (pad metal) openings of the 67 pads, 80 µm pitch. The ESD diodes and power clamps sit inboard of the pads at the top level (bottom and left edges of the full-chip image).

Digital core

12 cyclesone decision slot (SLOT_DIV)

3 264weight latch bits

+4.06 / +6.99 nssetup WNS (worst / best corner), 0 failing endpoints

30.9 mVworst dynamic supply drop (3.4 %)

Verification (sign-off) results

All runs were made on the delivered geometry. DRC and density were run on the filled database, LVS and antenna on the unfilled one (the fill is floating and electrically inert).

Check	Result	Date
DRC (full chip, filled)	1728 rules / 0 violations	26 Aug 2026
Density (OD, PO, M1–M9, AP; 89 rules)	0 violations	26 Aug 2026
LVS (full chip)	CORRECT — port names read from the pad labels	26 Aug 2026
Antenna (37 rules)	0 violations (re-run on 27 Aug against the 26 Aug geometry, identical)	27 Aug 2026
Wire-bond rules	0 violations	26 Aug 2026
ERC	2 findings → waiver requests (below)	26 Aug 2026
Static timing — setup (WC / BC)	WNS +4.063 / +6.993 ns, TNS 0, ±5 % OCV derate	26 Aug 2026
Static timing — hold	WNS −22 ps, 131 endpoints → waiver request	26 Aug 2026
Dynamic IR drop (real gate-level VCD)	30.9 mV = 3.4 %, 0 violations (no intentional on-chip decoupling)	26 Aug 2026

Waiver requests to the foundry: three items only

#	Item	Count	Nature
1	ERC "MOS connected to both power and ground"	270 results / 540 geometries	By design: the ESD clamps across four supply domains
2	ERC floating N-well	1	By design. Went 55 → 36 → 1; two were real defects and were fixed
3	Hold WNS	−22 ps / 131 endpoints	With ±5 % derate; no functional risk

DRC, LVS, antenna and wire-bond checks required no waivers.

Dummy fill: 6.25 million shapes

To satisfy the density rules, floating fill shapes connected to no net were added with an in-house generator to OD, PO, the nine metals and AP. The fill is entirely inside the die boundary. The filled database (chipfill.gds) is the submission candidate; the density rules are met only there.

All 89 density rules (OD, PO, M1–M9, AP; low and high limits) are clean on the filled database.

Layer	GDS	Shapes	Edge (µm)
DOD (diffusion dummy)	6;1	1 155 589	1.00
DPO (poly dummy)	17;1	1 164 918	0.80
DUM1 … DUM7	31;1 … 37;1	3 478 537	1.20
DUM8	38;1	336 893	1.60
DUM9	39;1	106 819	3.00
DAP (AP fill)	—	1 816	20.00
Total		6 247 548