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Three decks that explain the design. Click a thumbnail to browse at full size, or download the PDFs.

PPU Version A — ExplainedNoise and weights Q&APad labels

PPU Version A — Explained

Five questions, step-by-step answers, real circuits: what the noise source is, where the weights come from, and when each of them changes. 28 pages, 9 September 2026. Download PDF

Cover1. Cover The five questions and short answers2. The five questions and short answers The machine on one page3. The machine on one page The eFlash plan next to Version A4. The eFlash plan next to Version A Where the chip sits, what is on the die5. Where the chip sits, what is on the die Q2 answer: a standard-CMOS test ASIC6. Q2 answer: a standard-CMOS test ASIC Why an annealer needs noise7. Why an annealer needs noise What the noise must and must not do8. What the noise must and must not do Two noise sources: a timeline9. Two noise sources: a timeline What an LFSR is10. What an LFSR is One leg of the LFSR DAC11. One leg of the LFSR DAC Six legs together12. Six legs together Why the LFSR DAC was dropped13. Why the LFSR DAC was dropped What thermal noise is14. What thermal noise is The thermal chain, block by block15. The thermal chain, block by block Inside one gain stage16. Inside one gain stage Inside the steerer17. Inside the steerer How loud each code is (measured)18. How loud each code is (measured) Q4: when the noise changes19. Q4: when the noise changes How the sequencer steps the temperature20. How the sequencer steps the temperature Q4 answer21. Q4 answer Q5: how a problem gets into the chip22. Q5: how a problem gets into the chip How a stored weight becomes a current23. How a stored weight becomes a current Q5 answer24. Q5 answer Everything in one slot25. Everything in one slot Summary table26. Summary table Glossary27. Glossary Sources and dates28. Sources and dates

Noise source, weight loading and update timing

The same five questions, each answer preceded by the relevant block diagram or real circuit. 21 pages. Download PDF

Cover1. Cover The whole signal path2. The whole signal path Five questions, short answers3. Five questions, short answers Where the chip sits, what is on the die4. Where the chip sits, what is on the die What chip? A standard-CMOS test ASIC5. What chip? A standard-CMOS test ASIC Two noise sources side by side6. Two noise sources side by side Q1: two answers, one day apart7. Q1: two answers, one day apart LFSR DAC circuits8. LFSR DAC circuits The noise source as presented9. The noise source as presented The thermal chain and how loud each code is10. The thermal chain and how loud each code is The noise source as taped out11. The noise source as taped out When the noise changes12. When the noise changes Q4 answer13. Q4 answer How a problem gets into the chip14. How a problem gets into the chip Q5 answer15. Q5 answer Synapse cell circuit16. Synapse cell circuit Weight → current17. Weight → current One slot: from row select to spin update18. One slot: from row select to spin update The three blocks that turn two currents into one bit19. The three blocks that turn two currents into one bit One decision slot20. One decision slot Summary table21. Summary table

Pad labels and their functions

All 67 pads on three pages: digital/control, analog trim and reference, supplies/grounds/test. 10 September 2026. Download PDF

1/3 Digital & control (north, 27 pads)1. 1/3 Digital & control (north, 27 pads) 2/3 Analog trim & reference (west 18 + south 6)2. 2/3 Analog trim & reference (west 18 + south 6) 3/3 Supplies, grounds & test (east 8 + south 8)3. 3/3 Supplies, grounds & test (east 8 + south 8)